1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a domain crossing circuit of a semiconductor apparatus.
2. Related Art
Referring to FIG. 1, a conventional domain crossing circuit 1 of a semiconductor apparatus includes a first buffer (BUF) 10, a delay-locked loop block 20, a second buffer (BUF) 30, a command decoder (CMD DEC) 40, a command timing control block (CMD CTRL) 50, a latency control block 60, a clock enable block (CLKEN GEN) 70, an output timing control block (DQ CTRL) 80, and a transmission block (TX) 90.
The first buffer 10 receives an external clock signal CLK and outputs an internal clock signal ICLK.
The delay-locked loop block 20 is configured to output a delay-locked loop clock signal DLLCLK in response to the internal clock signal ICLK and a clock enable signal CLKEN.
The delay-locked loop block 20 outputs the delay-locked loop clock signal DLLCLK generated by correcting the delay time of the internal clock signal ICLK, in response to the clock enable signal
CLKEN, such that the phases of the internal clock signal ICLK and an output data signal are synchronized.
The delay-locked loop block 20 includes a variable delay line (Variable Delay Line) 21, a replica delay (Replica Delay) 22, a phase detector (Phase Detector) 23, a DLL controller (DLL CTRL) 24, and a driver (DRV) 25. The replica delay 22 being capable of receiving a feedback clock signal FBCLK.
The second buffer 30 receives a column address strobe signal CAS and outputs an internal column address strobe signal PCAS.
The command decoder 40 decodes the internal column address strobe signal PCAS, a row address strobe signal RAS and a write enable signal WE, and outputs a command signal.
The command timing control block 50 shifts the output signal of the command decoder 40 by an address latency (AL), and outputs a read command signal RDCMD.
The latency control block 60 generates a latency signal LATENCY and an enable period signal RDCLKEN in response to the read command signal RDCMD.
The latency control block 60 includes a variable delay line (Variable Delay Line) 61 and a shift block (Latency Shift) 62.
The variable delay line 61 delays the read command signal RDCMD by a varied delay time and outputs a read command delayed signal RDCMDD.
The shift block 62 shifts the read command delayed signal RDCMDD by a CAS latency (CL) on the basis of the delay-locked loop clock signal DLLCLK, and generates the latency signal LATENCY.
The clock enable block 70 generates the clock enable signal CLKEN in response to the internal clock signal ICLK, the read command signal RDCMD and the enable period signal RDCLKEN.
The output timing control block 80 controls the timing of the latency signal LATENCY by a preset value on the basis of the delay-locked loop clock signal DLLCLK, and outputs a resultant signal.
The transmission block 90 performs an operation of outputting data DQ (or DQ and DQS) (not illustrated) in response to the output signal of the output timing control block 80.
Operations of the conventional domain crossing circuit of a semiconductor apparatus configured as mentioned above will be described below with reference to FIG. 2 (see also FIG. 1).
The delay time from the external clock signal CLK to the delay-locked loop clock signal DLLCLK is tBUF+tVD+tDRV, (where tBUF is the delay time associated with the first buffer 10, tVD is the delay time associated with the variable delay line 21, and tDRV is the delay time associated with the driver 25) and the delay time from the column address strobe signal CAS to the read command delayed signal RDCMDD is tBUF+tCMD+tVD (where tBUF is the delay time associated with the second buffer 30, tCMD is the delay time associated with the command decoder 40 and the command timing control block 50, and tVD is the delay time associated with the variable delay line 61).
The delay time tDRV by the driver 25 is longer than the delay time tCMD by the command decoder 40 and the command timing control block 50.
Therefore, a timing margin tMARGIN decreases by tCMD-tDRV in the latency control block 60.
Additionally, FIGS. 1 and 2 illustrate a time delay associated with data tDQ with regards to the transmission block 90 and the output timing control block 80.
Further, the delay time from the external clock signal CLK to a delayed clock signal DCLK as the output signal of the variable delay line 21 is tBUF+tVD, whereas the delay time from the column address strobe signal CAS to the clock enable signal CLKEN is tBUF+tCMD+tCKEN (where tCKEN is the delay time associated with the clock enable block 70). Therefore, under the situation where tVD becomes very small and the inequality tVD<tCMD+tCKEN is satisfied, a time for generating the clock enable signal CLKEN is delayed, and thus, the first pulse of the delay-locked loop clock signal DLLCLK may have a very short activation period or may not be generated.
As a result, in the conventional art, a command (such as a read command, a write command, and the like) may not be precisely aligned with a clock signal, that is, the delay-locked loop clock signal DLLCLK, and the data output performance of the semiconductor apparatus may be degraded.